Coding and HDL

Waveform viewer

Read the signal graph that appears under a Verilog test case.

When you run Verilog sample tests, you can open a case and see its waveform: a graph of every signal over time.

What you see

One row per signal. A single-bit signal is drawn as a square wave. A multi-bit signal (a bus) is drawn as boxes with its value inside.
Unknown and high-impedance values (x and z) are shown in red.
A time axis with the timescale label.

Controls

Control	What it does
hex / dec / bin	Changes how bus values are shown.
Zoom in / out	Zoom up to 256 times.
Fit	Fits the whole simulation on screen.
Hover	A dashed cursor follows your mouse and the signal names column shows every signal's value at that time.

When you won't see a waveform

Waveforms are only produced for the sample cases of a run. Hidden tests don't produce them.
If a simulation is very long, you'll see "Long simulation: only the first part of the waveform is shown." The viewer keeps up to 64 signals, with a limit on how many changes it stores.

Not available

The viewer doesn't have draggable or pinned cursors, markers, or signal selection and reordering.

Verilog

How Verilog questions work: your module, the testbench, lint, and how you are graded.

SPICE

Describe a circuit as a netlist and have it simulated with ngspice.

On this page

What you see Controls When you won't see a waveform Not available